Automated manufacturing equipment has streamlined the manufacturing process in many industries. Moreover, such automation has increased reliability and results. A downside of automation has been timing delays in equipment operations. Particularly, where expensive manufacturing equipment is involved, delays in operations of the equipment, such as during mechanical movements in transferring devices under test, limits returns on the costs of such equipment because of idle or non-testing use periods during mechanical manipulations, resets, and the like. An impetus in manufacturing technology and operation has, therefore, been to limit times in which costly test equipment is idle and not performing the applicable test function.
In semiconductor manufacture, semiconductor device test equipment is a costly capital requirement. Conventionally, such test equipment has included a robotic manipulator for handling the devices being tested. This robotic manipulator is commonly referred to as a “handler” and is typically configured with one or more robotic arms referred to as “manipulators.” The manipulator mechanically picks up a device for testing, inserts the device into an interface test board and issues a start-of-test signal to the tester. The tester then conducts a test on the device and returns a test result and an end-of-test signal to the handler that causes the handler to disposition the device to a post-test tray or receptacle for holding tested devices. This process is repeated as long as the handler senses that there are additional devices available for test. This system as a whole is sometimes referred to as a “test cell.”
During the time required for the handler to disposition a device(s) just tested and replace the device(s) with the next device(s) to be tested, the tester remains substantially idle. This idle time sometimes referred to as “index time” for the particular tester and system, involves mechanical manipulations of the devices awaiting test and having been tested. These mechanical manipulations are limited in speed of operations by various factors, including, for example, physical and speed constraints to ensure that devices to be tested are not damaged, contaminated, dropped, and the like.
The time required to test a device is sometimes referred to as “test time” for a particular device, test, tester, and system. When the system is operational in a manufacturing capacity, it is either indexing during the index time or otherwise testing during the test time.
Previously, test equipment manufacturers have focused efforts to reduce index time on design of manufacturing equipment to increase speed of mechanical operations. Although speeds of mechanical operations in handling the test devices have increased significantly over time, there nonetheless remains significant mechanical index time required to manipulate test devices between tests, by the robotic handlers. Moreover, with increased speeds of mechanical manipulation equipment operations, costs increase for the equipment, including calibration, replacement frequency, maintenance, parts, and others. Given the constraints and precautions that must be addressed in speeding mechanical manipulations of many types of test devices and handlers, further speeding of mechanical operations is subject to economic and physical barriers.
In any event, reducing index time can provide greater returns on investments in test equipment, particularly where the test equipment is costly. It would therefore be a significant improvement in the art and the technology to further reduce index time involved in test operations in manufacturing environments. Particularly in semiconductor manufacture, economic and other gains and advantages are possible if index times are reduced in the testing of semiconductor equipment. It would also be an improvement to provide new and improved systems and methods for achieving reduced index times, without requiring substantial changes or new developments in existing mechanical operations of device handlers and similar robotic or automated components for the testing. Examples of recent advancements made by the present inventor in reducing index time for automated and robotic semiconductor testing are disclosed in other patents by the present inventor, including U.S. Pat. Nos. 7,183,785 B2, 7,508,191 B2, and 7,619,432 B2.
In addition to the advantages of reducing index times discussed above, it would also be an improvement to provide new and improved systems and methods for setting up and configuring the control systems for automated and robotic semiconductor test equipment, which further reduces the cost, complexity, index time, and downtime of testing operations associated with the automated and robotic semiconductor test equipment. For instance, conventional automated semiconductor test equipment is commonly serialized where each individual test is performed sequentially. The primary reasons for serialized testing include thermal issues that restrict the number and complexity of tests that can be conducted at one time, and the complexity of implementation for non-serialized testing. Additionally, conventional Design for Test (DFT) testing normally requires exclusive control of the testing device when running, thus preventing any other non-DFT test from being executed at the same time.
An illustration of a conventional standard flow test cell 100 is illustrated in FIG. 1A. The conventional standard flow test cell 100 traditionally includes an Automatic Test Equipment (ATE) Test System 101, which operates at a high speed and is characterized as having a high pin count. The conventional standard flow test cell 100 also traditionally includes a single socket Device Under Test (DUT) Board 102 that interfaces with a conventional handler 103. In the conventional standard flow test cell 100, untested semiconductor devices 104 are sequentially input into the conventional standard flow test cell 100, sequentially tested, and then sequentially output as tested semiconductor devices 105. An illustration of the sequential testing arrangement of a conventional standard flow test cell 100 is illustrated in FIG. 1B. FIG. 1B shows the sequential ordering of tests that are serially executed in a conventional standard flow test cell. As illustrated therein, the tests are sequentially ordered from the first test, Test 1, through the last test, Test N. FIG. 1C illustrates the sequential testing arrangement performing multiple different types of tests and including index time. The illustration shows a first period of index time, i.e., idle time. The index time is followed sequentially, by three periods during which three different types of tests are performed. During the second period, broadside digital tests are performed. During the third period, analog tests are performed. During the fourth period, design-for-test (DFT) tests are performed.
In the conventional standard flow test cell 100 described above, all semiconductor tests are serialized, with each successive test being performed in a set sequence. While the conventional standard flow test cell 100 provides certain advantages, it also has significant drawbacks. The advantages include being relatively simple to implement and having a short development time. It is also easy to maintain, debug, and modify, and runs on essentially all semiconductor test systems. However, the significant drawbacks include requiring a long test time due to the relatively poor utilization of the test cell's Automatic Test Equipment System 101. As a result, the conventional standard test cell 100 provides a low throughput resulting in high semiconductor test costs.